Computer Organization
Computer Arithmetic
Marks 1Marks 2Marks 5
Machine Instructions and Addressing Modes
Marks 1Marks 2
Memory Interfacing
Marks 1Marks 2Marks 5
IO Interface
Marks 1Marks 2
Alu Data Path and Control Unit
Marks 1Marks 2
Secondary Memory
Marks 1Marks 2
1
GATE CSE 2007
MCQ (Single Correct Answer)
+1
-0.3
Consider a $$4$$-way set associative cache consisting of $$128$$ lines with a line size of $$64$$ words. The $$CPU$$ generates a $$20$$-bit address of a word in main memory. The numbers of bits in the TAG, LINE and WORD fields are respectively
A
$$9,6,5$$
B
$$7,7,6$$
C
$$7,5,8$$
D
$$9, 5, 6$$
2
GATE CSE 2005
MCQ (Single Correct Answer)
+1
-0.3
Increasing the $$RAM$$ of a computer typically improves performance because
A
Virtual memory increases
B
Larger $$RAM$$s are faster
C
Fewer page faults occur
D
Fewer segmentation faults occur
3
GATE CSE 2001
MCQ (Single Correct Answer)
+1
-0.3
More than one word are put in one cache block to
A
Exploit the temporal locality of reference in a program
B
Exploit the spatial locality of reference in a program
C
Reduce the miss penalty
D
None of the above
4
GATE CSE 1999
MCQ (Single Correct Answer)
+1
-0.3
The main memory of a computer has $$2$$ $$cm$$ blocks while the cache has $$2$$ $$c$$ blocks. If the cache uses the set associative mapping scheme with $$2$$ blocks per set, then block $$k$$ of the main memory maps to the set:
A
($$k$$ mod $$m$$) of the cache
B
($$k$$ mod $$c$$) of the cache
C
($$k$$ mod $$2c$$) of the cache
D
($$k$$ mod $$2cm$$) of the cache
GATE CSE Subjects
Theory of Computation
Operating Systems
Algorithms
Digital Logic
Database Management System
Data Structures
Computer Networks
Software Engineering
Compiler Design
Web Technologies
General Aptitude
Discrete Mathematics
Programming Languages
Computer Organization