1
GATE CSE 1991
Numerical
+2
-0
Find the maximum clock frequency at which the counter in Fig., can be operated. Assume that the propagation delay through each flip-flop and $$AND$$ gate is $$10$$ $$ns.$$ Also assume that the setup time for the $$JK$$ inputs of the flip-flops is negligible.
Your input ____
Questions Asked from Marks 2
GATE CSE 2025 Set 1 (1) GATE CSE 2023 (1) GATE CSE 2022 (1) GATE CSE 2021 Set 2 (1) GATE CSE 2021 Set 1 (1) GATE CSE 2015 Set 1 (1) GATE CSE 2014 Set 3 (1) GATE CSE 2011 (2) GATE CSE 2009 (1) GATE CSE 2007 (1) GATE CSE 2006 (1) GATE CSE 2004 (1) GATE CSE 2003 (1) GATE CSE 2001 (2) GATE CSE 2000 (1) GATE CSE 1991 (1)
GATE CSE Subjects
Theory of Computation
Operating Systems
Algorithms
Digital Logic
Database Management System
Data Structures
Computer Networks
Software Engineering
Compiler Design
Web Technologies
General Aptitude
Discrete Mathematics
Programming Languages
Computer Organization