If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?

A $$4$$-way set-associative cache memory unit with a capacity of $$16KB$$ is built using a block size of $$8$$ words. The word length is $$32$$ bits. The size of the physical address space is $$4$$ $$GB.$$ The number of bit for the TAG field is ____________.

Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for $$100$$ nanoseconds ($$ns$$) by the data, address, and control signals. During the same $$100$$ $$ns$$, and for $$500$$ $$ns$$ thereafter, the addressed memory module executes one cycle accepting and storing the data. The (internal) operation of different memory modules may overlap in time, but only one request can be on the bus at any time. The maximum number of stores (of one word each) that can be initiated in $$1$$ millisecond is ____________.

A $$RAM$$ chip has a capacity of $$1024$$ words of $$8$$ bits each $$\left( {1K \times 8} \right).$$ The number of $$2 \times 4$$ decoders with enable line needed to construct a $$16K \times 16\,\,RAM$$ from $$1K \times 8\,\,RAM$$ is