Computer Organization
Computer Arithmetic
Marks 1Marks 2Marks 5
Machine Instructions and Addressing Modes
Marks 1Marks 2
Memory Interfacing
Marks 1Marks 2Marks 5
IO Interface
Marks 1Marks 2
Alu Data Path and Control Unit
Marks 1Marks 2
Secondary Memory
Marks 1Marks 2
1
GATE CSE 2016 Set 2
Numerical
+2
-0
A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The latency to read a block from the cache is $$1$$ $$ms$$ and to read a block from the disk is $$10$$ $$ms.$$ Assume that the cost of checking whether a block exists in the cache is negligible. Available cache sizes are in multiples of $$10$$ $$MB.$$ GATE CSE 2016 Set 2 Computer Organization - Memory Interfacing Question 21 English

The smallest cache size required to ensure an average read latency of less than $$6$$ $$ms$$ is _________ $$MB.$$

Your input ____
2
GATE CSE 2014 Set 3
Numerical
+2
-0
The memory access time is $$1$$ nanosecond for a read operation with a hit in cache, $$5$$ nanoseconds for a read operation with a miss in cache, $$2$$ nanoseconds for a write operation with a hit in cache and $$10$$ nanoseconds for a write operation with a miss in cache. Execution of a sequence of instructions involves $$100$$ instruction fetch operations, $$60$$ memory operand read operations and $$40$$ memory operand write operations. The cache hit-ratio is $$0.9.$$ The average memory access time (in nanoseconds) in executing the sequence of instructions is___________________.
Your input ____
3
GATE CSE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
In designing a computer’s cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?
A
A smaller block size implies better spatial locality
B
A smaller block size implies a smaller cache tag and hence lower cache tag overhead
C
A smaller block size implies a larger cache tag and hence lower cache hit time
D
A smaller block size incurs a lower cache miss penalty
4
GATE CSE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?
A
Width of tag comparator
B
Width of set index decoder
C
Width of way selection multiplexor
D
Width of processor to main memory data bus
GATE CSE Subjects
Theory of Computation
Operating Systems
Algorithms
Digital Logic
Database Management System
Data Structures
Computer Networks
Software Engineering
Compiler Design
Web Technologies
General Aptitude
Discrete Mathematics
Programming Languages
Computer Organization