Analog Electronics
Diode Circuits and Applications
Marks 1Marks 2Marks 5
Frequency Response
Marks 2
Bjt and Mosfet Biasing
Marks 1Marks 2Marks 5
Feedback Amplifiers and Oscillator Circuits
Marks 1Marks 2Marks 5
Operational Amplifier
Marks 1Marks 2Marks 5
Small Signal Modeling
Marks 1Marks 2Marks 5
1
GATE EE 2015 Set 1
MCQ (Single Correct Answer)
+2
-0.6
The op-amp shown in the figure has a finite gain $$A = 1000$$ and an infinite input resistance. A step voltage $${V_i} = 1\,\,mV$$ is applied at the input at time $$t = 0$$ as shown. Assuming that the operational amplifier is not saturated, the time constant (in millisecond) of the output voltage $${V_o}$$ is GATE EE 2015 Set 1 Analog Electronics - Operational Amplifier Question 22 English
A
$$1001$$
B
$$101$$
C
$$11$$
D
$$1$$
2
GATE EE 2015 Set 2
MCQ (Single Correct Answer)
+2
-0.6
The saturation voltage of the ideal op-amp shown below is $$ \pm 10\,V.$$ The output voltage $${V_O}$$ of the following circuit in the steady-state is GATE EE 2015 Set 2 Analog Electronics - Operational Amplifier Question 21 English
A
square wave of period $$0.55$$ $$ms.$$
B
triangular wave of period $$0.55$$ $$ms.$$
C
square wave of period $$0.25$$ $$ms. $$
D
triangular wave of period $$0.25$$ $$ms.$$
3
GATE EE 2014 Set 3
MCQ (Single Correct Answer)
+2
-0.6
The transfer characteristic of the Op-amp circuit shown in figure is GATE EE 2014 Set 3 Analog Electronics - Operational Amplifier Question 24 English
A
GATE EE 2014 Set 3 Analog Electronics - Operational Amplifier Question 24 English Option 1
B
GATE EE 2014 Set 3 Analog Electronics - Operational Amplifier Question 24 English Option 2
C
GATE EE 2014 Set 3 Analog Electronics - Operational Amplifier Question 24 English Option 3
D
GATE EE 2014 Set 3 Analog Electronics - Operational Amplifier Question 24 English Option 4
4
GATE EE 2014 Set 3
Numerical
+2
-0
A hysteresis type $$TTL$$ inverter is used to realize an oscillator in the circuit shown in the figure. GATE EE 2014 Set 3 Analog Electronics - Operational Amplifier Question 23 English

If the lower and upper trigger level voltages are $$0.9$$ $$V$$ and $$1.7$$ $$V,$$ the period (in $$ms$$), for which output is LOW, is ____________.

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GATE EE Subjects
Electromagnetic Fields
Signals and Systems
Engineering Mathematics
General Aptitude
Power Electronics
Power System Analysis
Analog Electronics
Control Systems
Digital Electronics
Electrical Machines
Electric Circuits
Electrical and Electronics Measurement