The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is

In the figure shown, the output ܻ is required to be ܻ Y=AB+ $$\overline C $$$$\overline D $$. The gates G1 and G2 must be, respectively,

In the circuit shown, diodes $${D_1}$$ ,$${D_2}$$ and $${D_3}$$ are ideal, and the inputs $${E_1}$$ , $${E_2}$$ and $${E_3}$$ are “0 V” for logic ‘0’ and “10 V” for logic ‘1’. What logic gate does the circuit represent?

In the circuit shown in the figure, if C = 0, the expression for Y is