Digital Electronics
Minimization
Marks 21
GATE EE 2024
MCQ (Single Correct Answer)
+1
-0.33
In the circuit, the present value of $Z$ is $1$. Neglecting the delay in the combinatorial circuit, the values of $S$ and $Z$, respectively, after the application of the clock will be
2
GATE EE 2022
Numerical
+1
-0
A MOD-2 and a MOD-5 up-counter when cascaded together results in a MOD _________ counter. (in integer).
Your input ____
3
GATE EE 2022
Numerical
+1
-0
The maximum clock frequency in MHz of a 4-stage ripple counter, utilizing flip-flops, with each flip-flop having a propagation delay of 20 ns, is ________. (round off to one decimal place).
Your input ____
4
GATE EE 2014 Set 3
MCQ (Single Correct Answer)
+1
-0.3
A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where $$X$$ is the don't care condition, and $$Q$$ is the output representing the state.
The logic gate represented by the state diagram is
Questions Asked from Marks 1
GATE EE Subjects
Electromagnetic Fields
Signals and Systems
Engineering Mathematics
General Aptitude
Power Electronics
Power System Analysis
Analog Electronics
Control Systems
Digital Electronics
Electrical Machines
Electric Circuits
Electrical and Electronics Measurement