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Digital Circuits
Number System and Code Convertions
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Boolean Algebra
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Logic Gates
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Combinational Circuits
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Sequential Circuits
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Semiconductor Memories
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Logic Families
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Analog to Digital and Digital to Analog Converters
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1
GATE ECE 2023
MCQ (Single Correct Answer)
+1
-0.33

In the circuit shown below, P and Q are the inputs. The logical function realized by the circuit shown below is

GATE ECE 2023 Digital Circuits - Combinational Circuits Question 4 English

A
Y = PQ
B
Y = P + Q
C
Y = $$\mathrm{\overline {PQ} }$$
D
Y = $$\mathrm{\overline {P+Q} }$$
2
GATE ECE 2022
MCQ (Single Correct Answer)
+1
-0.33

Consider the 2-bit multiplexer (MUX) shown in the figure. For OUTPUT to be the XOR of C and D, the values for A0, A1, A2 and A3 are ___________.

GATE ECE 2022 Digital Circuits - Combinational Circuits Question 5 English

A
A0 = 0, A1 = 0, A2 = 1, A3 = 1
B
A0 = 1, A1 = 0, A2 = 1, A3 = 0
C
A0 = 0, A1 = 1, A2 = 1, A3 = 0
D
A0 = 1, A1 = 1, A2 = 0, A3 = 0
3
GATE ECE 2017 Set 2
MCQ (Single Correct Answer)
+1
-0.3
Consider the circuit shown in the figure. GATE ECE 2017 Set 2 Digital Circuits - Combinational Circuits Question 38 English The Boolean expression F implemented by the circuit is
A
$$\overline X \,\overline Y \,\overline Z + XY + \,\overline Y \,Z$$
B
$$\overline X \,Y\,\overline Z + XZ + \,\overline Y \,Z$$
C
$$\overline X \,Y\,\overline Z + XY + \,\overline Y \,Z$$
D
$$\overline X \,\overline Y \,\overline Z + XZ + \,\overline Y \,Z$$
4
GATE ECE 2016 Set 2
MCQ (Single Correct Answer)
+1
-0.3
A 4:1 multiplexer is to be used for generating the output carry of a full adder. A and B are the bits to be added while 𝐶in is the input carry and 𝐶out is the output carry. A and B are to be used as the select bits with A being the more significant select bit. GATE ECE 2016 Set 2 Digital Circuits - Combinational Circuits Question 39 English Which one of the following statements correctly describes the choice of signals to be connected to the inputs $${I_0}$$, $${I_1}$$, $${I_2 }$$ and $${I_3}$$ so that the output is C$$_{out}$$?
A
$${I_0} = 0,{I_0} = {C_{in}},\,{I_{2\,}} = {C_{in}}\,and\,{I_3} = I$$
B
$${I_0} = 1,\,{I_1}\, = {C_{in}},\,{I_{2\,}} = {C_{in}}\,and\,{I_3} = I$$
C
$${I_0} = {C_{in}},\,\,{I_{1\,}} = 0,\,{I_{2\,}} = 1and\,{I_3} = \,{C_{in}}$$
D
$${I_0} = 0,{I_1} = {C_{in}},\,{I_{2\,}} = \,2and\,{I_3} = {C_{in}}\,$$
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GATE ECE 2025 (1) GATE ECE 2023 (1) GATE ECE 2022 (1) GATE ECE 2017 Set 2 (1) GATE ECE 2016 Set 2 (1) GATE ECE 2014 Set 2 (1) GATE ECE 2012 (1) GATE ECE 2011 (1) GATE ECE 2005 (1) GATE ECE 2003 (1) GATE ECE 1997 (1) GATE ECE 1995 (1) GATE ECE 1992 (1) GATE ECE 1990 (1)
GATE ECE Subjects
Signals and Systems
Network Theory
Control Systems
Digital Circuits
General Aptitude
Electronic Devices and VLSI
Analog Circuits
Engineering Mathematics
Microprocessors
Communications
Electromagnetics