Digital Circuits
1
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
For the NMOS logic gate shown in figure, the logic function implemented is
2
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because
3
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
The inverter 74AL SO4 has the following specifications:
$${I_{OH}}{\,_{\max \,}} = \, - $$ 0.4mA, $${I_{OL}}$$ max = 8mA, $${I_{IH}}$$ max = $$\mu $$A , $${I_{IL\,}}_{\max \,}$$=0.1mA. The fan out based on the above will be
$${I_{OH}}{\,_{\max \,}} = \, - $$ 0.4mA, $${I_{OL}}$$ max = 8mA, $${I_{IH}}$$ max = $$\mu $$A , $${I_{IL\,}}_{\max \,}$$=0.1mA. The fan out based on the above will be
4
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
In standard TTL the 'totem pole' stage refers to
GATE ECE Subjects
Signals and Systems
Network Theory
Control Systems
Digital Circuits
General Aptitude
Electronic Devices and VLSI
Analog Circuits
Engineering Mathematics
Microprocessors
Communications
Electromagnetics