Digital Electronics
Minimization
Marks 21
GATE EE 1995
Fill in the Blanks
+1
-0
For a $$J$$-$$K$$ flip-flop its $$J$$ input is tied to its own $$Q$$ output and its $$K$$ input is connected to its own $$Q$$ output. If the flip-flop is fed with a clock of frequency $$1$$ $$MHz,$$ its $$Q$$ output frequency will be ______________
Questions Asked from Marks 1
GATE EE Subjects
Electromagnetic Fields
Signals and Systems
Engineering Mathematics
General Aptitude
Power Electronics
Power System Analysis
Analog Electronics
Control Systems
Digital Electronics
Electrical Machines
Electric Circuits
Electrical and Electronics Measurement