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Digital Circuits
Number System and Code Convertions
Marks 1Marks 2
Boolean Algebra
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Logic Gates
Marks 1Marks 2Marks 5Marks 8
Combinational Circuits
Marks 1Marks 2Marks 5Marks 8Marks 10
Sequential Circuits
Marks 1Marks 2Marks 5Marks 8
Semiconductor Memories
Marks 1Marks 2
Logic Families
Marks 1Marks 2Marks 8
Analog to Digital and Digital to Analog Converters
Marks 1Marks 2
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1
GATE ECE 2004
MCQ (Single Correct Answer)
+1
-0.3
Figure shows the internal schematic of a TTL AND-OR-Invert (AOI) gate. For the inputs shown in Figure, the output Y is GATE ECE 2004 Digital Circuits - Logic Families Question 13 English
A
0
B
1V
C
AB
D
$$\overline {AB} $$
2
GATE ECE 2003
MCQ (Single Correct Answer)
+1
-0.3
The output of the 74 series of TTL gates is taken from a BJT in
A
Totem pole and common collector configuration
B
either totem pole or open collector configuration
C
common base configuration
D
common collector configuration
3
GATE ECE 1999
MCQ (Single Correct Answer)
+1
-0.3
Commercially available ECL gates use two ground lines and one negative supply in order to
A
reduce power dissipation
B
increase fan-out
C
reduce loading effect
D
eliminate the effect of power line glitches or the biasing circuit.
4
GATE ECE 1999
MCQ (Single Correct Answer)
+1
-0.3
A Darlington Emitter follower circuit is sometimes used in the output stage of a TTL gate in order to
A
increase its $${I_{OL}}$$
B
Reduce its $${I_{OH}}$$
C
Increase its speed of operation.
D
Reduce power Dissipation.
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Questions Asked from Marks 1
GATE ECE 2022 (1) GATE ECE 2014 Set 4 (1) GATE ECE 2009 (1) GATE ECE 2005 (2) GATE ECE 2004 (1) GATE ECE 2003 (1) GATE ECE 1999 (2) GATE ECE 1998 (2) GATE ECE 1997 (4) GATE ECE 1992 (1) GATE ECE 1991 (2) GATE ECE 1989 (2) GATE ECE 1987 (1)
GATE ECE Subjects
Signals and Systems
Network Theory
Control Systems
Digital Circuits
General Aptitude
Electronic Devices and VLSI
Analog Circuits
Engineering Mathematics
Microprocessors
Communications
Electromagnetics