Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor 𝑅 = 10 𝑘Ω and the supply voltage is 5 𝑉. The D flip-flops D₁, D₂, D₃, D₄ and D₅ are initialized with logic values 0, 1, 0,1 and 0, respectively. The clock has a 30% duty cycle.

The average power dissipated (in mW) in resistor R is ______.

A mod-n counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of n is _______.

The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset ($$\overline {{R_d}} $$ input). The counter corresponding to this circuit is

Five JK flip - flops are cascaded to form circuit shown in figure. Clock pulses at a frequency of 1 MHz are applied as shown. The frequency (in kHz) of the waveform at Q₃ is ______.