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Microprocessors
Pin Details of 8085 and Interfacing with 8085
Marks 1Marks 2
Instruction Set and Programming with 8085
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1
GATE ECE 1998
MCQ (Single Correct Answer)
+1
-0.3
An I/O processor control the flow of information between
A
cache memory and I/O devices
B
main memory and I/O devices
C
two I/O devices
D
cache and main memories
2
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
In an 8085$$\mu$$P system, the RST instruction will cause an interrupt
A
only if an interrupt service routine is not being executed
B
only if a bit in the interrupt mask is made 0
C
only if interrupts have been enabled by an EI instruction
D
None of the above
3
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
The decoding circuit shown below has been used to generate the active low chip select signal for a microprocessor peripheral. (The address lines are designated as $${A_0}$$ to $${A_7}$$ for I-O address) GATE ECE 1997 Microprocessors - Pin Details of 8085 and Interfacing with 8085 Question 3 English
A
60 H to H
B
A 4 H to A7 H
C
50 H to AF H
D
70 H to 73 H
4
GATE ECE 1995
MCQ (Single Correct Answer)
+1
-0.3
In a microprocessor, when a CPU is interrupted, it
A
Stops execution of instructions.
B
Acknowledges interrupt and branches of subroutine.
C
Acknowledges interrupt and continues.
D
Acknowledges interrupt and waits for the next instrution from the interrupting device.
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Questions Asked from Marks 1
GATE ECE 2010 (2) GATE ECE 2000 (2) GATE ECE 1999 (1) GATE ECE 1998 (1) GATE ECE 1997 (2) GATE ECE 1995 (1) GATE ECE 1993 (1) GATE ECE 1992 (1) GATE ECE 1988 (3)
GATE ECE Subjects
Signals and Systems
Network Theory
Control Systems
Digital Circuits
General Aptitude
Electronic Devices and VLSI
Analog Circuits
Engineering Mathematics
Microprocessors
Communications
Electromagnetics