Digital Circuits
1
GATE ECE 2015 Set 3
MCQ (Single Correct Answer)
+2
-0.6
A three bit pseudo random number generator is shown. Initially the value of output Y = Y2 Y1 Y0 is set to 111. The value of output Y after three clock cycles is
2
GATE ECE 2015 Set 3
MCQ (Single Correct Answer)
+2
-0.6
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing
3
GATE ECE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms
W1, W2, W3 and W4.
4
GATE ECE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0, 0. The sequence
generated at Q1 upon application of clock signal is
Questions Asked from Marks 2
GATE ECE 2025 (2) GATE ECE 2024 (1) GATE ECE 2023 (1) GATE ECE 2022 (2) GATE ECE 2018 (1) GATE ECE 2017 Set 1 (2) GATE ECE 2017 Set 2 (1) GATE ECE 2016 Set 2 (2) GATE ECE 2015 Set 2 (1) GATE ECE 2015 Set 3 (2) GATE ECE 2014 Set 2 (2) GATE ECE 2014 Set 1 (1) GATE ECE 2012 (1) GATE ECE 2011 (2) GATE ECE 2009 (1) GATE ECE 2008 (1) GATE ECE 2007 (2) GATE ECE 2006 (1) GATE ECE 2004 (1) GATE ECE 2003 (1) GATE ECE 2001 (1) GATE ECE 2000 (2) GATE ECE 1999 (1) GATE ECE 1998 (1)
GATE ECE Subjects
Signals and Systems
Network Theory
Control Systems
Digital Circuits
General Aptitude
Electronic Devices and VLSI
Analog Circuits
Engineering Mathematics
Microprocessors
Communications
Electromagnetics