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1
GATE ECE 1991
Fill in the Blanks
+1
-0
A SR FLIP-FLOP can be converted into a T FLIP-FLOP by connecting ___ to Q and ___ to $$\overline Q $$.
2
GATE ECE 1990
MCQ (Single Correct Answer)
+1
-0.3
A 4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 50ns, the maximum clock frequency that can be used is equal to:
A
20 MHz
B
10 MHz
C
5 MHz
D
4 MHz
3
GATE ECE 1988
MCQ (Single Correct Answer)
+1
-0.3
The circuit given below is a GATE ECE 1988 Digital Circuits - Sequential Circuits Question 11 English
A
J-K Flip-flop
B
Johnson's counter
C
R-S latch
D
None of above
4
GATE ECE 1987
MCQ (Single Correct Answer)
+1
-0.3
A ripple counter using negative edge-triggered D-flip flops is shown in Fig.1. The flip-flops are cleared to '0' by a '0' at the R input. The feedback logic is to be designed to obtain the count sequence shown in the same figure. The correct feedback logic is: GATE ECE 1987 Digital Circuits - Sequential Circuits Question 14 English 1 GATE ECE 1987 Digital Circuits - Sequential Circuits Question 14 English 2
A
$$F\, = \overline {{Q_2}{Q_1}\overline {{Q_0}} } $$
B
$$F\, = \,{Q_2}\,\overline {{Q_1}} \overline {{Q_0}} $$
C
$$F\, = \,\overline {{Q_2}} \overline {{Q_1}} {Q_0}$$
D
$$F\, = \,\overline {{Q_2}} \overline {{Q_1}} \overline {{Q_0}} $$
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Questions Asked from Marks 1
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GATE ECE Subjects
Signals and Systems
Network Theory
Control Systems
Digital Circuits
General Aptitude
Electronic Devices and VLSI
Analog Circuits
Engineering Mathematics
Microprocessors
Communications
Electromagnetics