Digital Circuits
1
GATE ECE 1996
Subjective
+5
-0
A 4-bit shift register, which shifts 1 bit to the right at every clock pulse, is intialized to values (1000) for (Q0Q1Q2Q3). The D input is derived from Q0, Q2 and Q3 through two XOR gates as shown in figure.
(a) Write the 4-bit values (Q0Q1Q2Q3) after each clock pulse till the pattern (1000) reappears on (Q0Q1Q2Q3).
(b) To what values should the shift register be intialized so that the pattern (1001) occurs after the first clock pulse?
Questions Asked from Marks 5
GATE ECE Subjects
Signals and Systems
Network Theory
Control Systems
Digital Circuits
General Aptitude
Electronic Devices and VLSI
Analog Circuits
Engineering Mathematics
Microprocessors
Communications
Electromagnetics