IC Basics and MOSFET
Practice QuestionsMarks 1
1
For a MOS capacitor, $$\mathrm{V_{fb}}$$ and $$\mathrm{V_{t}}$$ are the flat-band voltage and the threshold voltage, respectively. The variation of the depletion width ($$\mathrm{W_{dep}}$$) for varying gate voltage ($$\mathrm{V_{g}}$$) is best represented by
GATE ECE 2023
2
For the circuit shown in the figure, P and Q are the inputs and Y is the output.
The logic implemented by the circuit is
The logic implemented by the circuit is
GATE ECE 2017 Set 2
3
Consider an n-channel MOSFET having width W, length L, electron mobility in the channel
$$\mu_n$$ and oxide capacitance per unit area $$C_{ox}$$. If gate-to-source voltage VGS=0.7 V, drain-to source
voltage VDS=0.1V, $$\left(\mu_nC_{ox}\right)\;=\;100\;\mu A/V^2$$, threshold voltage VTH=0.3 V and (W/L) = 50,
then the transconductance gm (in mA/V) is ___________.
GATE ECE 2017 Set 2
4
An n-channel enhancement mode MOSFET is biased at VGS > VTH and VDS > (VGS - VTH), where
VGS is the gate-to-source voltage, VDS is the drain-to-source voltage and VTH is the threshold
voltage. Considering channel length modulation effect to be significant, the MOSFET behaves
as a
GATE ECE 2017 Set 2
5
The figure shows the band diagram of a Metal Oxide Semiconductor (MOS). The surface region of
this MOS is in
GATE ECE 2016 Set 3
6
Transistor geometries in a CMOS inverter have been adjusted to meet the requirement for
worst case charge and discharge times for driving a load capacitor C. This design is to be
converted to that of a NOR circuit in the same technology, so that its worst case charge and
discharge times while driving the same capacitor are similar. The channel lengths of all
transistors are to be kept unchanged. Which one of the following statements is correct?
GATE ECE 2016 Set 2
7
A long-channel NMOS transistor is biased in the linear region with VDS = 50 mV and is used
as a resistance. Which one of the following statements is NOT correct?
GATE ECE 2016 Set 2
8
Consider the following statements for a metal oxide semiconductor field effect transistor
(MOSFET):
P: As channel length reduces, OFF-state current increases.
Q:As channel length reduces, output resistance increases.
R: As channel length reduces, threshold voltage remains constant.
S: As channel length reduces, ON current increases.
GATE ECE 2016 Set 1
9
What is the voltage Vout in the following circuit?
GATE ECE 2016 Set 1
10
Which one of the following processes is preferred to from the gate dielectric (SiO2) of
MOSFETs?
GATE ECE 2015 Set 3
11
In the ac equivalent circuit shown in the figure, if in is the input current and RF is very large, the type of feedback
GATE ECE 2014 Set 1
12
If fixed positive charges are present in the gate oxide of an n-channel enhancement type
MOSFET, it will lead to
GATE ECE 2014 Set 1
13
In the following circuit employing pass transistor logic, all NMOS transistors are identical
with a threshold voltage of 1 V. Ignoring the body-effect, the output voltages at P, Q and R
are,
GATE ECE 2014 Set 1
14
In MOSFET fabrication, the channel length is defined during the process of
GATE ECE 2014 Set 3
15
In CMOS technology, shallow P-well or N-well regions can be formed using
GATE ECE 2014 Set 2
16
In a MOSFET operating in the saturation region, the channel length modulation
effect causes
GATE ECE 2013
17
In IC technology, dry oxidation (using dry oxygen) as compared to wet oxidation
(using steam or water vapor) produces
GATE ECE 2013
18
In the circuit shown
GATE ECE 2012
19
In the circuit shown below, for the MOS transistors, $$\mu_nC_{ox}\;=\;100\;\mu A/V^2$$ and the
threshold voltage VT = 1 V. The voltage Vx at the source of the upper transistor is
GATE ECE 2011
20
The drain current of a MOSFET in saturation is given by $$I_D\;=\;K\left(V_{GS}\;-V_T\right)^2$$ where 'K'
is a constant. The magnitude of the transconductance gm is
GATE ECE 2008
21
A silicon wafer has 100 mm of oxide on it and is inserted in a furnace at a
temperature above 1000ºC for further oxidation in dry oxygen. The oxidation
rate
GATE ECE 2008
22
A MOS capacitor made using p-type substrate is in the accumulation mode. The
dominant charge in the channel is due to the presence of
GATE ECE 2005
23
Consider the following statements S1 and S2.
S1: The threshold voltage (VT) of a MOS capacitor decreases with increase in gate
oxide thickness
S2: The threshold voltage (VT) of a MOS capacitor decreases with increase in
substrate doping concentration.
GATE ECE 2004
24
The threshold voltage of an n-channel MOSFET can be increased by
GATE ECE 1994
Marks 2
1
Consider a MOS capacitor made with p-type silicon. It has an oxide thickness of 100 nm, a fixed positive oxide charge of $10^{-8}$ C/cm2 at the oxide-silicon interface, and a metal work function of 4.6 eV. Assume that the relative permittivity of the oxide is 4 and the absolute permittivity of free space is $8.85 × 10^{-14}$ F/cm. If the flatband voltage is 0 V, the work function of the p-type silicon (in eV, rounded off to two decimal places) is ______.
GATE ECE 2024
2
In the circuit below, the voltage V$$_{\mathrm{L}}$$ is _____________ V (rounded off to two decimal places).
GATE ECE 2023
3
Two n-channel MOSFETs, T1 and T2, are identical in all respects except that the width of T2 is double of T1. Both the transistor are biased in the saturation region of operation, but the gate overdrive voltage (VGS - VTH) of T2 is double that of T1, where VGS and VTH are the gate-to-source voltage and threshold voltage of the transistors, respectively. If the drain current and transconductance of T1 are ID1 and gm1 respectively ; the corresponding values of these two parameters for T2 are
GATE ECE 2017 Set 2
4
Assuming that transistor M1 and M2 are identical and have a threshold voltage of 1V, the state of transistors M1 and M2 are respectively
GATE ECE 2017 Set 2
5
A MOS capacitor is fabricated on p-type Si (silicon) where the metal work function is 4.1 eV
and electron affinity of Si is 4.0 eV, Ec - EF = 0.9 eV; where Ec and EF are conduction band minimum and the Fermi energy levels of Si, respectively. Oxide$${\varepsilon _r} = \,\,3.9,\,\,\,{\varepsilon _{0\,\,}}=\,8.85 \times {10^{ - 14}}$$ F/cm, oxide thickness $${t_{ox}} = 0.1\,\mu m$$
and electronic charge q = $$1.6 \times {10^{ - 19}}$$ C. If the measured flat band
voltage of the capacitor is –1V, then the magnitude of the fixed charge at the oxide semiconductor
interface, in nC/cm2, is __________.
GATE ECE 2017 Set 2
6
For the circuit shown, assume that the NMOS transistor is in saturation. Its threshold voltage
Vtn = 1 V and its trans-conductance parameter $${\mu _n}{C_{ox}}\left( {{W \over L}} \right) = 1m{\rm A}/{V^2}.$$ Neglect channel length modulation and body bias effects. Under these conditions the drain current ID in mA is______.
GATE ECE 2017 Set 1
7
Figures $${\rm I}$$ and $${\rm I}{\rm I}$$ show two MOS capacitor of unit area. The capacitor in Figure I has insulator materials X (of thickness t1 = 1 nm and dielectric constant $${\varepsilon _1}$$ = 4) and Y (of thickness t2 =3 nm and dielectric constant $${\varepsilon _2}$$ = 200). The capacitor in Figure $${\rm I}{\rm I}$$ has only insulator material X of thickness teq. If the capacitors are of equal capacitance, then the value of teq (in nm) is ______
GATE ECE 2016 Set 3
8
In the circuit shown in the figure, the channel length modulation of all transistors is non-zero $$\left( {\lambda \ne 0} \right)$$. Also all transistors operate in saturation and have negligible body effect. The ac small
signal voltage gain $$\left( {{V_0}/{V_{in}}} \right)$$ of the circuit is
GATE ECE 2016 Set 3
9
In the circuit shown in the figure, transistor M1 is in saturation and has transconductance
gm = 0.01 siemens. Ignoring internal parasitic capacitances and assuming the channel length
modulation $$\lambda $$ to be zero, the small signal input pole frequency (in kHz) is _____
GATE ECE 2016 Set 3
10
Consider a long-channel NMOS transistor with source and body connected together. Assume that
the electron mobility is independent of VGS and VDS. Given,
gm = 0.5$$\mu {\rm A}/V$$ for VDS = 50 m V and VGS = 2V,
gd = $$8\mu {\rm A}/V$$ for VGS = 2 V and VDS = 0 V,
Where gm =$${{\partial {{\rm I}_D}} \over {\partial {V_{GS}}}}\,\,and\,\,{g_d}\,\, = \,{{\partial {{\rm I}_D}} \over {\partial {V_{DS}}}}$$
gm = 0.5$$\mu {\rm A}/V$$ for VDS = 50 m V and VGS = 2V,
gd = $$8\mu {\rm A}/V$$ for VGS = 2 V and VDS = 0 V,
Where gm =$${{\partial {{\rm I}_D}} \over {\partial {V_{GS}}}}\,\,and\,\,{g_d}\,\, = \,{{\partial {{\rm I}_D}} \over {\partial {V_{DS}}}}$$
The threshold voltage (in volts) of the transistor is
GATE ECE 2016 Set 2
11
A voltage VG is applied across a MOS capacitor with metal gate and p-type silicon substrate at
T=300 K. The inversion carrier density (in number of carriers per unit area) for VG = 0.8 V is $$2\,\, \times \,\,{10^{11}}\,\,\,\,\,\,c{m^{ - 2}}$$ . For $${V_G}\,\, = \,\,1.3\,\,V,$$ the inversion carrier density is $$4\,\,\, \times \,\,\,{10^{11}}\,\,\,\,c{m^{ - 2}}.$$ What is the value of the inversion carrier density for VG = 1.8 V?
GATE ECE 2016 Set 2
12
Consider an n-channel metal oxide semiconductor field effect transistor (MOSFET) with a gate-to-source
voltage of 1.8 V. Assume that $${W \over L} = 4,{\mu _{\rm N}}{C_{ox}} = 70 \times {10^{ - 6}}{\rm A}{V^{ - 2}}$$ , the threshold voltage is 0.3V, and the channel length modulation parameter is 0.09 V-1, In the saturation region, the drain conductance (in micro siemens) is__________.
GATE ECE 2016 Set 1
13
In a MOS capacitor with an oxide layer thickness of 10 nm, the maximum depletion layer thickness is 100 nm. The permittivities of the semiconductor and the oxide layer are $${\varepsilon _s}$$ and $${\varepsilon _{os}}$$ respectively. Asuuming $${\varepsilon _s}/{\varepsilon _{ox}} = 3$$ , the ratio of the maximum capacitance to the minimum capacitance of this MOS capacitor is________
GATE ECE 2015 Set 2
14
In the circuit shown, both the enhancement mode NMOS transistors have the following characteristics: kn = $${\mu _n}{C_{ox}}(W/L) = 1m{\rm A}/{V^2}$$ ; VTN = 1V. Asuume that the channel length modulation parameter $$\lambda $$ is zero and body is shorted to source. The minimum supply voltage VDD (in volts) needed to ensure that transistor M1 operates in saturation mode of operation is _____
GATE ECE 2015 Set 3
15
The current in an enhancement mode NMOS transistor biased in saturation mode was measured to be 1 mA at a drain-source voltage of 5 V. When the drain-source voltage was increased to 6 V while keeping gate-source voltage same, the drain current increased to 1.02 mA. Assume that drain to source saturation voltage is much smaller than the applied drain-source voltage. The channel length modulation p[arameter $$\lambda $$ (in V-1) is _______
GATE ECE 2015 Set 3
16
A MOSFET in saturation has a drain current of 1 mA for VDS =0.5V. If the channel length modulation coefficient is 0.05 V-1, the output resistance (in k$$\Omega $$) of the MOSFET is______
GATE ECE 2015 Set 1
17
For the NMOSFET in the circuit shown, in the threshold voltage is Vth, where Vth>0. The source voltage Vss is varied from 0 to VDD. Neglecting the channel length modulation, the drain current ID as a function of Vss is represented by
GATE ECE 2015 Set 1
18
A depletion type N -channel MOSFET is biased in its linear region for use as a voltage controlled resistor. Assume threshold voltage VTH = -0.5 V, VGS = 2.0 V, VDS = 5 V, W/L=100, COX=10-8 F/cm2 and $${\mu _n}$$ = 800 cm2/V-s. The value of the resistance of the voltage controlled resistor (in $$\Omega $$ ) is _____.
GATE ECE 2014 Set 1
19
The slope of the ID vs. VGS curve of an n-channel MOSFET in linear region is 10-3$${\Omega ^{ - 1}}$$ at VDS = 0.1V. For the same device, neglecting channel length modulation, the slope of the $$\sqrt {{{\rm I}_D}} $$ vs. V GS curve (in $$\sqrt A /V$$ ) under saturation region is approximately ______.
GATE ECE 2014 Set 3
20
An ideal MOS capacitor has boron doping concentration of 1015 cm-3 in the substrate. When a gate voltage is applied, a depletion region of width 0.5 $$\mu m$$ is formed with a surface (channel) potential of 0.2V. Given that $${\varepsilon _0} = 80854 \times {10^{ - 14}}F/cm$$ and the relative permittivities of silicon and silicon dioxide are 12 and 4, respectively, the peak electric field (in V/ $$\mu m$$ ) in the oxide region is ______
GATE ECE 2014 Set 3
21
For the MOSFET M1 shown in the figure, assume W/L =2, VDD = 2.0 V, $$\mu n$$ COX = 100$$\mu {\rm A}/{V^2}$$ and VTH =0.5 V. The transistor M1 switches from saturation region to linear regionm when Vin(in Volts) is _____
GATE ECE 2014 Set 3
22
For the MOSFETs shown in the figure, the threshold voltage |Vt| = 2V and
K=$${1 \over 2}\mu {C_{OX}}\left( {{W \over L}} \right) = 0.1mA/{V^2}$$ . The value of ID (in mA) is _______
K=$${1 \over 2}\mu {C_{OX}}\left( {{W \over L}} \right) = 0.1mA/{V^2}$$ . The value of ID (in mA) is _______
GATE ECE 2014 Set 2
23
For the n-channel MOS transistor shown in the figure, the threshold voltage VTh is 0.8V. Neglect channel length modulation effects. When the drain voltage VD = 1.6 V, the drain current ID was found to be 0.5 mA.
GATE ECE 2014 Set 2
24
The small-signal resistance (i.e., $${{d{V_B}} \over {d{I_D}}}$$ ) in $$k\Omega $$ offered by the n-channel MOSFET M shown in the figure below, at bias point of VB = 2V is (device data for M: device transconductance parameter
kN = $${\mu _n}{C_{ox}^{'}}$$ (W/L)= 40$$\mu {\rm A}/{V^2},$$ threshold voltage VTN=1V, and neglect body effect and channel length modulation effects)
GATE ECE 2013
25
In the three dimensional view of a silicon n-channel MOS transistor shown below, $$\delta = 20$$ nm. The transistor is of width 1 $$\mu m$$. The depletion width formed at every p-n junction is 10 nm. The relative permittivities of Si and SiO2, respectively, are 11.7 and 3.9, and $${\varepsilon _0}$$ = 8.9 $$ \times {10^{ - 12}}$$ F/m.
The source-body junction capacitance is approximately
GATE ECE 2012
26
The source of a silicon (ni = 1010 per cm3) n - channel MOS transistor has an aewa of 1 sq $$\mu m$$ and a depth of 1 $$\mu m$$ . If the dopant density in the source is 1019/cm3, the number of holes in the source region with the above volume is approximately
GATE ECE 2012
27
In the three dimensional view of a silicon n-channel MOS transistor shown below, $$\delta = 20$$ nm. The transistor is of width 1 $$\mu m$$. The depletion width formed at every p-n junction is 10 nm. The relative permittivities of Si and SiO2, respectively, are 11.7 and 3.9, and $${\varepsilon _0}$$ = 8.9 $$ \times {10^{ - 12}}$$ F/m.
The gate-source overlap capacitance is approximately
GATE ECE 2012
28
In the CMOS circuit shown, electron and hole mobilities are equal, and M1 and M2 are equally sized. The device M1 is in the linear region if
GATE ECE 2012
29
Consider the CMOS circuit shown, where the gate voltage of the n-MOSFET is increased
from zero, while the gate voltage of the p-MOSFET is kept constant at 3 V. Assume that, for
both transistors, the magnitude of the threshold voltage is 1 V and the product of the
transconductance parameter and the $$\left(\frac WL\right)$$ ratio, i.e. the quantity $$\mu C_{ox}\left(\frac WL\right)$$ , is 1 mAV-2.
Estimate the output voltage V0 for VG =1.5 V. [Hints: Use the appropriate current-voltage equation for each MOSFET, based on the answer]
Estimate the output voltage V0 for VG =1.5 V. [Hints: Use the appropriate current-voltage equation for each MOSFET, based on the answer]
GATE ECE 2009
30
Consider the CMOS circuit shown, where the gate voltage of the n-MOSFET is increased
from zero, while the gate voltage of the p-MOSFET is kept constant at 3 V. Assume that, for
both transistors, the magnitude of the threshold voltage is 1 V and the product of the
transconductance parameter and the $$\left(\frac WL\right)$$ ratio, i.e. the quantity $$\mu C_{ox}\left(\frac WL\right)$$ , is 1 mAV-2.
For small increase in VG beyond 1 V, which of the following gives the correct description of the region of operation of each MOSFET?
For small increase in VG beyond 1 V, which of the following gives the correct description of the region of operation of each MOSFET?
GATE ECE 2009
31
The measured transconductance gm of an NMOS transistor operating in the linear
region is plotted against the gate voltage VG at constant drain voltage VD. Which
of the following figures represents the expected dependence of gm on VG?
GATE ECE 2008
32
For the circuit shown in the following figure, transistors M1 and M2 are identical
NMOS transistors. Assume that M2 is in saturation and the output is unloaded
The current Ix is related to Ibias as
The current Ix is related to Ibias asGATE ECE 2008
33
Two identical NMOS transistors M1 and M2 are connected as shown below. Vbias is
chosen so that both transistors are in saturation. The equivalent gm of the pair is
defined to be $$\frac{\partial I_{out}}{\partial v_i}$$
at constant Vout.
The equivalent gm of the pair is
GATE ECE 2008
34
In the CMOS inverter circuit shown, if the transconductance parameters of the
NMOS and PMOS transistors are
Kn = Kp = μnCOX$$\frac{W_n}{L_n}$$ = μpCOX$$\frac{W_P}{L_P}$$= 40 μA/V2 and their threshold voltages are VT = 1 V, the current I is:
Kn = Kp = μnCOX$$\frac{W_n}{L_n}$$ = μpCOX$$\frac{W_P}{L_P}$$= 40 μA/V2 and their threshold voltages are VT = 1 V, the current I is:
GATE ECE 2007
35
An n-channel depletion MOSFET has following two points on its ID − VGS curve:
(i) VGS = 0 at ID = 12 mA and
(ii) VGS = - 6 Volts at ID = 0
Which of the following Q-points will give the highest trans-conductance gain for small signals?
(i) VGS = 0 at ID = 12 mA and
(ii) VGS = - 6 Volts at ID = 0
Which of the following Q-points will give the highest trans-conductance gain for small signals?
GATE ECE 2006
36
The drain of an n-channel MOSFET is shorted to the gate so that VGS = VDS. The
threshold voltage (VT) of MOSFET is 1 V. If the drain current (ID) is 1 mA for VGS =
2 V, then for VGS = 3 V, ID is
GATE ECE 2004
37
If P is Passivation, Q is n-well implant, R is metallization and S is source/drain
diffusion, then the order in which they are carried out in a standard n-well CMOS
fabrication process, is
GATE ECE 2003
38
When the gate-to-source voltage (VGS) of a MOSFET with threshold voltage of
400 mV, working in saturation is 900 mV, the drain current is observed to be 1
mA. Neglecting the channel width modulation effect and assuming that the
MOSFET is operating at saturation, the drain current for an applied VGS of 1400
mV is
GATE ECE 2003
39
For an n-channel enhancement type MOSFET, if the source is connected at a
higher potential than that of the bulk (i.e. VSB > 0), the threshold voltage VT of
the MOSFET will
GATE ECE 2003