A 10-bit analog-to-digital converter (ADC) has a sampling frequency of 1 MHz and a full scale voltage of 3.3 V . For an input sinusoidal signal with frequency 500 kHz , the maximum SNR (in dB, rounded off to two decimal places) and the data rate (in Mbps) at the output of the ADC are _________ , respectively.

Consider the circuit shown with an ideal OPAMP. The output voltage V₀ is __________ V (rounded off to two decimal places).

In an N bit flash ADC, the analog voltage is fed simultaneously to 2^N− 1 comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source V_in(whose output is being converted to digital format) has a source resistance of 75 Ω as shown in the circuit diagram below and the input capacitance of each comparator is 8 pF. The input must settle to an accuracy of 1/2 LSB even for a full scale input change for properconversion. Assume that the time taken by the thermometer to binary encoder is negligible. If the flash ADC has 8 bit resolution, which one of the following alternatives is closest to the maximum sampling rate?